void spi_read(float* q,int n) {
   Xuint8 Buffer[2];
   Xuint8 Out[2];
   Xuint32 data,Control;

   int NumBytesSent = 2;
   int NumBytesRcvd = 2;
   int i,j;

   //poll spi mic
   for(i=0;i<n;i++) {
	NumBytesSent = 0;
	NumBytesRcvd = 0;

	//set slave select to high
	XSpi_mSetSlaveSelectReg(BaseAddress, 0xFFFFFFFF);

	/*set options for spi device
	manual_SS_mask: user controls which slave select bit to enable
	enable_mask: enables spi device
	master_mode_mask: sets the spi device in master mode
	trans_inhibit_mask: inhibits transaction of data
	*/
	Control=XSP_CR_MANUAL_SS_MASK | XSP_CR_ENABLE_MASK | XSP_CR_MASTER_MODE_MASK |
				XSP_CR_TRANS_INHIBIT_MASK;
	XSpi_mSetControlReg(BaseAddress, Control);
		
	//fill outgoing FIFO buffer with data
	for(j=0;j<2;j++) 
		XSpi_mSendByte(BaseAddress, Out[NumBytesSent++]);

	//enable slave select
	XSpi_mSetSlaveSelectReg(BaseAddress, 0xFFFFFFFE);
	//turn off transaction ihibit
	Control &= ~XSP_CR_TRANS_INHIBIT_MASK;
	XSpi_mSetControlReg(BaseAddress, Control);
			
	/*
	* Wait for the transmit FIFO to transition to empty before checking
	* the receive FIFO, this prevents a fast processor from seeing the
	* receive FIFO as empty
	*/
	while (!(XSpi_mGetStatusReg(BaseAddress) & XSP_SR_TX_EMPTY_MASK)) {}

	/*
	* Transmitter is full, now receive the data just looped back until
	* the receiver is empty.
	*/
	while ((XSpi_mGetStatusReg(BaseAddress) & XSP_SR_RX_EMPTY_MASK) == 0)
		Buffer[NumBytesRcvd++] = XSpi_mRecvByte(BaseAddress);
		
	//convert data to floating point voltage		
	data=Buffer[0];
	data=data<<8;
	data=data+Buffer[1];
	q[i]=data/16;

	//set transaction inhibit
	Control |= XSP_CR_TRANS_INHIBIT_MASK;
		XSpi_mSetControlReg(BaseAddress, Control);		
	}
}


